The phase locked loop (PLL) is a basic component of radio, telecommunication and wireless technologies. PLLs are used for frequency control in a wide variety of applications, and, for example, can be configured as frequency multipliers, tracking generators, demodulators or clock recovery circuits. FIG. 1 is a block diagram showing a basic analog PLL, configured as a frequency multiplier. As can be seen, it is basically a feedback control system that controls a voltage controlled oscillator (VCO) 12. An AC signal having a reference frequency Fin is provided to one input of a phase detector 14. The other input of the phase detector 14 is taken from the output of a divide by N counter 16. The output of the phase detector 14 is typically a varying DC signal having a voltage that is proportional to the phase difference between the two inputs. This signal is provided to a loop filter 18 which determines certain dynamic characteristics of the PLL. The filtered signal is applied to the input of the VCO 12, and controls its phase. The output of the VCO 12 is provided as the output signal of the PLL, and is also provided to the input of the divide by N counter 16 as a feedback signal. During normal operation, the PLL controls the frequency Fout of the output signal to be N times Fin, the frequency multiplication occurring as a result of the operation of the divide by N counter 16.
The loop filter 18 is typically designed to provide the characteristics required for the application of the PLL. For example, if the PLL is intended to acquire and track a signal, the loop filter is usually designed to provide a greater bandwidth than if it were intended to be used in an application in which the input frequency is known to be within a narrow range. Other factors bear on the decision of what bandwidth to select for a given application of a PLL. For example, low loop bandwidths typically require that the PLL include a large, external compensation capacitor, which can be in the range of 0.01–1 μF. Such a large capacitor provided externally adds cost to a design. In addition, PLLs in wireless phones are constantly being powered down and back up to save power. It can take a PLL having a large external compensation capacitor up to 10 ms to power up, which is not acceptable to many wireless phone manufacturers.
However, CODECs for wireless phones with multiple formats, such as GSM, TDMA, CDMA, etc., must be capable of acquiring and tracking multiple input reference frequencies, with low noise characteristics, to properly decode and process the transmitted information. The multitude of frequencies requires that the common divisor reference frequency be low, which requires that the loop bandwidth be low, typically 0.1 times the reference frequency. This creates the possibility that an undesirable, large external compensation capacitor be used.
One prior art approach to meeting low bandwidth requirements, while avoiding the external compensation capacitor, is the all digital PLL (ADPLL). In the ADPLL, all functional blocks are implemented by entirely digital circuits. A large number of digital blocks can be used to implement an all digital PLL. Typically, an ADPLL requires two external clocks. FIG. 2 shows an example of one arrangement of digital blocks forming an ADPLL 20. A digital phase detector 24 receives an AC signal having a reference frequency fin at one input. Phase detector 24 can be implemented, for example, as an exclusive OR (XOR) gate. The other input of the phase detector 24 is taken from the output of a divide by N counter 26, which is the output of the ADPLL and has a frequency fout. Phase detector 24 compares the phase of the incoming signal with the phase of the output signal, and outputs an error signal having a frequency proportional to the phase difference, i.e., fin−fout. The output of the phase detector 24 is provided to a down/not-up (D/Ū) input of a K-counter 28. K-counter 28 also receives a clock signal CLK at a clock input, and outputs a carry signal at a CA output and a borrow signal at a BO output. K-counter 28 consists of an up-counter and a down-counter, with respective carry and borrow outputs. The D/Ū input to K-counter 28 controls which half of the counter (up or down) is in operation. The carry and borrow outputs of K-counter 28 are connected to respective increment and decrement inputs to an increment/decrement (I/D) circuit 22. The I/D circuit 22 also has as an input a reference clock signal at a frequency 2Nfc, where fc is the free running frequency of the ADPLL when no input is applied. The I/D circuit 22 produces an output signal at a frequency of half of the reference clock signal when no increment or decrement is in progress. A pulse to the decrement input of I/D circuit 22 causes one half-cycle to be deleted from the I/D circuit 22 output, while a pulse to the increment input results in a half cycle being added to that output. The output of the I/D circuit 22 is provided to the input of the divide by N counter 26.
In operation, when the inputs to the phase detector 24 are such that its output is low, then the up-counter of the K-counter 28 operates, eventually producing a carry pulse. The carry pulse is provided to the increment input of I/D circuit 22, causing one half cycle to be added to the output of I/D circuit 22. On the other hand, when the output of phase detector 24 is high, then the down-counter of the K-counter 28 operates, eventually producing a borrow pulse. The borrow pulse is provided to the decrement input of I/D circuit 22, causing one half cycle to be deleted from the output of I/D circuit 22. This continues, so that in a lock state, a specific phase difference is maintained between fin and fout. By selecting a high modulus K for the K-counter 28, a low bandwidth can be provided.
As can be seen from the above example, using an ADPLL eliminates the external compensation capacitor. However, ADPLLs have high noise and jitter characteristics. In addition, intermittent glitches can occur in ADPLLs because of quantization and race conditions due to delays that add and subtract at different output frequencies.
Another prior art approach to meeting low bandwidth requirements, while avoiding the external compensation capacitor, is a hybrid analog/digital phase locked loop (DPLL) using a variable delay line. FIG. 3 shows such a DPLL circuit 30. The circuit includes a first variable delay 31, a second variable delay 32, a set-reset flip-flop 33, a ΔΣ phase comparator 34, a frequency divider (by m) 35 and a delay controller 36 which is a finite state machine. The output signal CK×m is taken from the output of inverter 37 which has its input taken from the output of frequency divider 35. The input clock signal CK, output signal CK×m, and signals at nodes A, R, J and M of FIG. 3 are shown in FIG. 4. To aid in understanding, in FIG. 4 is arbitrarily set at the value six; in practice it can vary widely, depending on the application.
Referring now to FIGS. 3 and 4, in operation, a rising transition on CK at the set 0 input of flip-flop 33 creates a “set” condition for flip-flop 33, resulting in a rising edge at node A, as shown at 41 in FIG. 4. This transition propagates through variable delay 31 and variable delay 32, each of which is set to a delay of duration τ. Since node R is connected to the reset input of flip-flop 33, after a delay of τ after the rising transition on CK flip-flop 33 is reset, causing the signal at node A to fall to a low level, as shown at 42 in FIG. 4. At a time τ after that, the rising edge at node J at the set 1 input of flip-flop 33 creates another “set” condition for flip-flop 33, resulting in another rising edge at node A, as shown at 43 in FIG. 4. These events recur during m cycles, which are counted by the frequency divider 35. When node M goes high (44 in FIG. 4) the s0 input of the multiplexer at the input of flip-flop 33 is selected, resulting in the circuit selecting the external signal CK. At the mth cycle, the phase comparator 34 measures the displacement between the rising edge of CK 45 and the signal on node J 46. A signal corresponding to this measured displacement is provided to the delay controller 36, which adjusts the values of the delay τ so as to maintain lock. The arrangement shown in FIG. 3 has a quantization error of two least significant bits (LSBs).
The range of variation in the delay τ in the arrangement of FIG. 3 is sufficiently wide to allow the circuit to work between the maximum frequency, fmax, and fmax/2. To reduce the output frequency even further, a frequency divider can be added. An independent finite state machine may be provided to compare successive results of phase comparison to indicate whether or not the loop is locked.
Designers have chosen another variation of the DPLL approach to accommodate requirements such as wide range of input clock frequency, low power supply voltage and wide processing and temperature variations. The DPLL runs entirely in the digital domain, except for the Phase-Frequency-Detector (PFD), the time digitizer (T2D) and Digital-Controlled-Oscillator (DCO). Traditionally, a T2D circuit is used to convert the phase error into digital code. A problem arises when the input clock frequency varies by two orders of magnitude. Then the design of the T2D delay chain becomes more challenging. The T2D must prevent the phase error pulse from saturating the delay chain while occupying a small silicon area as well as maintaining low power consumption. Consequently, a variation of the DPLL has been developed to deal with this problem, which is shown in FIG. 5. This circuit uses a non-linear T2D delay chain 51, along with a corresponding lookup table 52, in addition to the usual input N-Divider 53, PFD 54, Digital Controller 55, DCO 56, Autodivider 57 and feedback M-Divider 58, with the output clock CLKOUT being taken from the output of Autodivider 57. This allows the phase error pulse to be measured and represented in more a meaningful and accurate way.
The circuit shown in FIG. 5 has a phase error resolution limit because of quantization (50 picoseconds) and a spurious signal problem because there is limited or even no filtering of the toggling bits going into the DCO 56. Furthermore, there is intermittent behavior due to adding and subtracting delays that change with input frequency, process and temperature.
FIG. 6 shows a hybrid prior art solution having a loop filter that uses a type 2 digital filter for a coarse tune, but uses a type 1 pulsed analog filter for a fine tune. The coarse tune loop is through an integrator 61 having an integration constant KI, while the fine tune loop is through a proportional analog converter 62 having a proportionality constant KP. The integrator 61 converts a phase error signal from Phase Detector 63 to a current CCOINT corresponding to the integral of the phase error over time. The analog converter 62 converts the phase error signal from Phase Detector 63 to a series of current pulses CCOPROP corresponding proportionally to the phase error. The signals CCOINT and CCOPROP are summed in Summer 64 to generate the sum signal CCO_TOTAL, which is provided to a Current Controlled Oscillator (CCO) 65, the output of which is a signal having a frequency fout and which is the PLL output. The output of CCO 65 is also provided to a Divide by N Scaler 66, the output of which, DIVOUT, is provided as the feedback signal to one input of Phase Detector 63. The other input of Phase Detector 63 is a reference signal having a frequency fin. The pulses of the fine tune analog converter 62 cause high jitter and high nose, which makes it undesirable for CODEC and other high performance applications.
FIG. 7 shows a hybrid prior art approach that uses a digital-to-analog converter (DAC) with Look-Up Table 71 to do a coarse tune and an analog filter using a charge pump 72 to do a fine tune, for its loop filter. An Up/Down counter may be used in the place of the Look-Up Table 71. A phase error signal from a Phase Detector 73 is provided to both the DAC/Look-Up Table 71 and Charge Pump Filter 72, with a fine tune signal from the Charge Pump Filter 72 and a coarse tune signal from the DAC/Look-Up Table 71 being provided to respective inputs of a Summer 74, providing a summed output CCO_TOTAL to a CCO 75, the output of which is the PLL output. The output of CCO 75 is also provided to a Divide by N frequency divider 76, the output of which is a signal having a frequency fout and which is provided as the feedback signal to one input of Phase Detector 73. The other input of Phase Detector 73 is a reference signal having a frequency fin. In the circuit arrangement of FIG. 7, the analog performance is maintained as long as the DAC does not switch. However, when such a switch occurs, a noise pulse is generated. In addition, a look-up table requires calibration to eliminate process effects and some calculations to minimize temperature and voltage effects. Up and down counting of the DAC also causes glitches and an uncertain response to disturbances such as power brown-outs from pulsing the power amplifier, and the like.